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UA Life Science Research - BioGate
Ali Akoglu
Assistant Professor
Contact Information
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Address: Electrical and Computer Engineering Department,
High Performance Embedded Computing Lab
University of Arizona
Tucson, AZ 85721
Phone: (520)626-5149
E-Mail: akoglu@ece.arizona.edu
Degrees
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Ph.D., Arizona State University 2005
B.S., Purdue University 1998
Department Affiliations
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Electrical & Computer Engineering, BIO5 Institute
Research Interests
Overview
Scope:
- High performance embedded computing with a primary focus on application specific architecture design space for compute intensive applications.
Objective:
- Respond to the ever growing computation demand through the design of much needed affordable high performance computing resources with faster number crunching capability
- Help scientists improve the quality of experiments in the process of comparing and searching for new protein structures
Current Research Activities:
- Designing reconfigurable architectures tailored to the computation characteristics of scientific applications
- Mapping biological systems and their computational methods onto those architectures
Technology Falls Short For Scientific Computing
- High-throughput technologies have led to an exponential growth in the amount of data generated in the fields of geophysics, biosciences, signal processing, computational fluid dynamics, and image and video processing over the past several years.This data explosion is forcing scientists to search for innovative computational designs to meet the growing demands.
- The complexity, variety of techniques and tools, and the high computation, storage and I/O bandwidths associated with these applications pose several challenges, particularly from the points of scalability, resource utilization (in terms of area and energy) and real-time implementation.
- Current technologies fall short of providing affordable and flexible architectures in responding to processing demand.
- These drawbacks have led us into application specific reconfigurable embedded systems tailored to the computation characteristics of the target applications.
Solution Space: Application Specific Reconfigurable Architectures
- Configurable computers based on FPGAs (Field Programmable Gate Arrays) are capable of accelerating suitable applications by several orders of magnitude when compared to traditional processor based architectures.
- There is evidence that reconfigurable systems can deliver 10X to 100X or greater improvement in computational efficiency for many computationally intensive problems by tailoring hardware allocations to match the needs of applications.
- This significant speed advantage is due to the highly parallel nature of FPGA hardware.
- Fortunately, many problems in those application domains listed above are inherently parallel, and can benefit from concurrent computing models.
Major Problem: Software
- Most software developers are not familiar with hardware design languages. This limits the ability of designers to utilize reconfigurable platforms.
- Existing hardware description languages themselves do not have the potential for making the transition from procedural to structural thinking that is required for hardware design,
- Programming languages such as SystemC, Handel-C, and Impulse-C allow designers to create system architectures and hardware components, and then implement the system’s application software in a semi-automated manner.
- However, system architecture and hardware design require advanced hardware design expertise.
- Programming FPGAs has historically been an extremely time-consuming process, requiring low-level design languages such as VHDL or Verilog.
- Therefore, there is a need for software solutions that provide a seamless transition between application software and the final hardware architecture. This can be accomplished through the development of “architecture development vehicle” software platforms that enable:
- Seamless algorithm design at a high level of abstraction,
- Execution at a high level of efficiency in hardware,
- Synthesizing layers of parallel execution structures all the way to the gate level without the need for unwieldy hardware assembly languages such as VHDL,
- Exploiting inherent parallelism at function level instead of program level with reusable libraries of functions.
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